Clock synchronization is necessary for many applications in communication networks. Clock synchronization protocols use a master clocks and timestamp information transmitted over packets to synchronize other nodes in the network. Specifically, 1588 Precision Time Protocol (PTP) uses hierarchical master-slave architecture and utilizes the internet to pass its packets to and from the slave nodes. PTP packets carry master timestamps to slave nodes where complex phase lock loops (PLLs) and filters recover the master clock and the 64 b timer associated with it.
PTP uses Sync, Delay_Req and Delay_Resp messages to advertise the master clock time and measure the (assumed) bi-directional delay. This delay is required to keep the nodes synchronized with the Master clock 64b timer and not only syntonized (i.e. being of the same tone, or in other words, being of the same frequency but not necessarily of the same phase) with its clock frequency.
Some applications such as cellular communications require sub microsecond synchronization of their respective clocks. PTP and other network synchronization protocols are especially vulnerable to variable/asymmetric delays and node congestion, as these are not taken into account in the delay calculations. To this end, 1588 v2 has an option for each PTP packet to measure its residence time, i.e. the time it takes each PTP packet to traverse a network element. These times are sometimes ignored during the delay calculation, effectively removing variable delays from the network. These element-wise residence time measurements require all packet passing elements within a node, to maintain a synchronized timer for packet time-stamping.
In a usual telecommunication node, a distributed architecture consisting of many elements is common, where each element plays a part in the switching/routing and management process. Though processing of the PTP packets and recreation of the master clock can be done on a regular processor with the required SW stack, precise reproduction of the PTP clock requires specialized and expensive HW. Due to this, it is common in distributed systems to have all the PTP packets routed to one element which reproduces the clock and distributes it to all the other elements in the distributed system. Since all the packet-passing elements need to maintain a timer synchronized with the PTP element, different information may be distributed to all the packet processing nodes, for example, a PTP clock (recovered from the PTP packets by the PTP HW), a once-per-second pulse (called 1PPS), and sometimes Time Of Day (TOD).
Distributing the master clock to all elements in a distributed system is costly in backplane and chip resources; its only aim to maintain the per-element 32 b/64 b ns timer needed to record ingress and egress packet times. Routing clocks around to maintain timers in all packet processing nodes is a burden on often loaded clock routing resources and may not be possible in legacy boards fitted with new FPGA logic and aiming to comply with strict PTP specifications.